Design of Convolutional Neural Network with Cuckoo Search Algorithm for Super-Resolution UHD Systems on FPGA

Abstract

Ultra high definition (UHD) video is considered as a technology that generates a video image with a resolution 16 times as many pixels as high definition television. Extensive and complex computational difficulties are there to generate a video in super-resolution (SR). Some extensive floating-point computations are needed for the direct implementation of area-pixel scaling, which is a factor for calculating one target pixel. In this paper, a hybrid Convolutional Neural Network and Cuckoo Search (CNN-CS) algorithm are proposed, which can replace the large scale of complex training and time-consuming machine learning technique. Cuckoo Search (CS) algorithm is based on bird’s levy-flight approach that can optimize the CNN. CS forecasting model isolates the redundant or irrelevant image patches and, therefore, it reduces the required memory space. The SR is performed effectively in hardware with less hardware utilization and memory space, where LR input data are processed line-by-line using the proposed hybrid CNN-CS algorithm. To optimize the design constraints, CS forecasting model estimates the required patches. Parallel sub pipeline (PSP) technique improves the parallelism process thereby reducing the computational complexity and improving the throughput rate and speed of execution. Finally, the proposed hybrid CNN-CS SR design is coded in Verilog HDL and is implemented with the XCKU040 FPGA device. To validate the proposed CNN-CS SR algorithm, standard datasets, such as Set-5, Set-14, BS-100 and Urban-100, are used. The visual quality of the proposed CNN-CS SR design is evaluated by the standard evaluation metrics such as peak signal-to-noise ratio (PSNR) and SSIM. The proposed hybrid CNN-CS SR design is compared with the existing state-of-the-art techniques both qualitatively and quantitatively. Experimental results demonstrate that the proposed method improved the throughput of 42.83%, memory space and power consumption are reduced to 16.16%, 63.81%, respectively, over the existing techniques.