Low Power Squaring Circuit Using Single Voltage Differencing Buffered Amplifier

Abstract

In this paper, a squaring circuit is proposed using a voltage differencing buffered amplifier (VDBA). The squaring circuit consists of a VDBA, two NMOS transistors and one resistor. The proposed structure facilitates easy cascading without any requirement of additional buffer. The behavior of the proposed structure is analyzed in the presence of nonidealities of VDBA and the corresponding mathematical formulations are also presented. The workability of the proposed circuit is verified through Cadence Virtuoso Analog Design Environment tool using 0.18[Formula: see text][Formula: see text]m generic process design kit parameters. Both pre- and post-layout simulation results have been included to confirm the functionality of the proposed circuit. The 3-dB frequency of the proposed circuit using schematic and post-layout-driven simulations is observed to be 3.77 and 3.72[Formula: see text]MHz, respectively. The power consumption of the proposed squaring circuit is found to be 110[Formula: see text][Formula: see text]W. The process, voltage and temperature (PVT) analysis has also been carried out to check the robustness of the proposed circuit. Total harmonic distortion for the entire input range is found to be less than 3%.