An Ultra-Low-Power C-Band FMCW Transmitter Using a Fast Settling Fractional-N DPLL and Ring-Based Pulse Injection Locking Oscillator

Author:

Muqueem Abdul1ORCID,Saxena Shanky1,Patel Govind Singh2

Affiliation:

1. VLSI Design, School of Electronics & Electrical Engineering, Lovely Professional University, Punjab 144411, India

2. Electronics and Computer Engineering, SITCOE, Yadrav, Kolhapur, Maharashtra, India

Abstract

Frequency-modulated continuous-wave (FMCW) signals-based radar systems can outrun the optical and ultrasound sensors in dark and severe weather conditions. FMCW radar systems require a fast settling frequency synthesizer to reduce the chirp signal’s inactive and modulation times. This work proposes a new C-B and FMCW Transmitter based on Fast Settling Fractional-N DPLL (FS-FNDPLL) and ring-based pulse injection locking oscillator (R-PILO). The proposed FS-FNDPLL generates an ultra-fast low-noise smooth narrowband chirp by introducing an automatic controller-based TDC switching (AC-TDCSw) scheme in the forward loop of FNDPLL. Also, the proposed FS-FNDPLL employs a new background gain calibrated digital-to-time converter (BGC-DTC) as a fractional divider in the feedback path for the quantization noise cancellation (QNC). The proposed FMCW transmitter uses an R-PILO to produce fast switching adjacent carriers after generating a narrowband chirp using FS-FNDPLL. The main features of the proposed FMCW to accelerate settling time with AC-TDCSw, BGC-DTC and the integration of spur suppressing pulse generator (SSPG) in R-PILO enable ultra-fast chirps with less phase noise and spur levels. The proposed transmitter up-converts the 500[Formula: see text]MHz narrowband chirp signal onto four adjacent carriers for obtaining a 2[Formula: see text]GHz chirp at the C-band. The simulation results prove that the proposed FMCW Transmitter consumes 79[Formula: see text]mW power. Furthermore, the phase noise of the proposed FS-FNDPLL is reduced to [Formula: see text][Formula: see text]dBc/Hz at 1[Formula: see text]MHz. The proposed FS-FNDPLL reduces the settling time to 1[Formula: see text][Formula: see text]s with the introduced AC-TDCSw scheme.

Publisher

World Scientific Pub Co Pte Ltd

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Media Technology

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