EFFECTS OF PARAMETER VARIATIONS ON TIMING CHARACTERISTICS OF CLOCKED REGISTERS-Reference-Cited by-同舟云学术

EFFECTS OF PARAMETER VARIATIONS ON TIMING CHARACTERISTICS OF CLOCKED REGISTERS

Published:2009-11 Issue:07 Volume:18 Page:1309-1320
ISSN:0218-1266
Container-title:Journal of Circuits, Systems and Computers
language:en
Short-container-title:J CIRCUIT SYST COMP

Author:

ROBERTS WILLIAM R.¹,VELENIS DIMITRIOS²

Affiliation:

1. TAC Corporation, One High Street, North Andover, MA 01845, USA

2. Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York, 14627, USA

Abstract

Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of parameter variations on the timing characteristics of registers that determine the timing constraints are investigated in this paper. The sensitivity of the setup time and data propagation delay to variations in power supply voltage, temperature, and gate oxide thickness is demonstrated for four different register designs. Furthermore, design modifications are proposed that enhance the robustness of each register to variation effects.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Link

https://www.worldscientific.com/doi/pdf/10.1142/S0218126609005678

Reference9 articles.

1. Timing Optimization Through Clock Skew Scheduling

2. Effect of parameter variations at chip and wafer level on clock skews

3. Delay and noise estimation of CMOS logic gates driving coupled resistive–capacitive interconnections

4. Device parameter changes caused by manufacturing fluctuations of deep submicron MOSFET's