Design of Low Power Speech Processor-Based Cochlear Implants Using Modified FIR Filter with Variable Frequency Mapping

Abstract

Generally, cochlear implant system consists of one or more electrodes which directly activate the auditory nerve. The microphone transforms external speech processor input into stimuli for each electrode and transcutaneous the connection between the electrodes and processor. As a result, cochlear implants continue to improve the performance of speech processor. After the implantation, preservation gains importance in acoustic hearing to prevent the neural degradation from the loss of cells. Eventually, the possibility of preserving low-frequency and high-frequency hearing using modified surgical technique has been explored for hearing in cochlear implantation. The primary focus on the architecture is to reduce the major potential thread performance and power trade-off. So, frequency mapping function with modified FIR filter has been proposed. For this implementation, the values relative to the frequency range defines upper and lower stimulus limits of each electrode. The proposed FIR filter is designed with distributed arithmetic function where the reconfigurable FIR filter can change the filter input coefficients. By scaling both the frequency ranges and by assessing the deriving frequency parameters, the mapping function will be yielded. Mapping function is manipulated to rectify any mapping deviations. This results in favor of the development of frequency specific mapping function with flexible system. From the proposed results, it is evident that the speech recognition performance is improved significantly by better minimization of overall energy consumption based on effective and pipelined FFT architecture. This implementation also reduces the power and improves the accuracy by 90% and above for different frequency ranges.