ARTIFICIAL NEURAL COMPUTATIONS IN DIGITAL ARRAYS

Abstract

In this paper the properties of artificial neural network computations by digital VLSI systems are discussed. We also comment on artificial computational models, learning algorithms, and digital implementations of ANNs in general. The analysis applies to regular arrays or processing elements performing binary integer arithmetic at various bit precisions. Computation rates are limited by power dissipation which is dependent upon required precision and packaging constraints such as pinout. They also depend strongly on the minimum feature size of the CMOS technology. Custom digital implementations with low bit precision are emphasized, because these circuits require less power and silicon area. This may be achieved using stochastic arithmetic, with pseudorandom number generation using cellular automata.