A 5.5-GHz Low-Power Divide-By-8/9 Dual Modulus Prescaler Using Pulse Extension Logic

Author:

Kumar Ravi1ORCID,Bohara Pooja1,Thakur Krishna2,Vishvakarma Santosh Kumar1ORCID

Affiliation:

1. NSDCS Lab, Department of Electrical Engineering, Indian Institute of Technology Indore, Madhya Pradesh 453552, India

2. MSIP-IDC, NXP Semiconductors, Noida, Uttar Pradesh, India

Abstract

This paper presents a new optimized high-speed divide-by-8/9 dual modulus prescaler. Simulation results show 54% reduction in power consumption, 40% of speed improvement and almost 48% area reduction as compared to the conventional architecture. Power consumption in the proposed prescaler is reduced by eliminating one True-Single-Phase Clocked (TSPC) D Flip-Flop (DFF) from the standard divide-by-2/3 prescaler, replacing it with Pulse Extension Logic (PEL) circuit. Redundant stages from asynchronous divide-by-2 units were also removed to save more power and reduce more delay. The simulation results show that the prescaler is capable of running at 5.5[Formula: see text]GHz of maximum frequency with 1.9[Formula: see text]mW power consumption. The divider is implemented in 0.18[Formula: see text][Formula: see text]m CMOS technology with 1.8[Formula: see text]V power supply.

Funder

Department of Electronics and Information Technology, Ministry of Communications and Information Technology

Publisher

World Scientific Pub Co Pte Ltd

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Media Technology

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