A Low Noise Sub-Gigahertz Fractional-N Frequency Generator with Cascaded FIR

Abstract

This paper proposes a low sub-gigahertz frequency generator with fine frequency resolution. An injection-locked ring oscillator (ILRO) is firstly adopted to obtain multiphase output at integer multiple times crystal oscillator (XO) frequency. Following that, a multiplexer (MUX) selects the output phase according to the output of a delta-sigma modulator ([Formula: see text]M) to achieve high frequency, low in-band noise fractional output. A hybrid type finite impulse response (FIR) filter, which is composed of some MUXs, flip-flops (FFs), digitally-controlled delay units (DCDUs), and a linear multiphase combiner (MPC), is employed in cascading to suppress the quantization noise (Q-noise) at high-frequency offset. An auto-calibration scheme for calibrating the DCDU’s delay has been proposed as well. Simulated in 65[Formula: see text]nm CMOS, the proposed fractional-N frequency generator exhibits a phase noise performance that is well below [Formula: see text]118[Formula: see text]dBc/Hz from 100[Formula: see text]kHz to 100[Formula: see text]MHz offset. The simulation also shows that the power consumption and die area is 10.6[Formula: see text]mW and 0.3[Formula: see text]mm2, respectively, with the FIR filter consuming 4.3[Formula: see text]mW and 0.041[Formula: see text]mm2.