FPGA-Based Multiplier-Less Log-Based Hardware Architectures for Hybrid Color Image Enhancement System

Abstract

Logarithmic image processing (LIP) models provide a viable framework for image enhancement, particularly the color-based models. These techniques, due to their vector nature, avoid the problems of grayscale methods applied to RGB color image processing. Furthermore, the absence of multiply-accumulate (MAC) operations makes them amenable to hardware realization for faster operation when compared with spatial filter kernel-based approaches. However, details of image scenes are not always revealed after processing and homomorphic filters are still a popular low-complexity option for correction of images acquired under uneven illumination conditions, notwithstanding the fading that occurs when processing RGB color images. Though nonlinear color space converter hardware architectures have been implemented and reported in the literature for improving results from conventional illumination correction techniques, they add to the hardware complexity. The contributions of the work described in this paper includes original, practical, standard and logarithmic, multiplier-less high-speed architectures for a variant of the LIP model in addition to standard and log-hybrid architectures for a modified spatial homomorphic filter (MSDHF) to reduce color fading in RGB space. The modified homomorphic filter is able to enhance both faded/bright and dark low-contrast images, giving it an edge over standard illumination correction systems. A combined approach utilizing the MSDHF and simplified LIP algorithms enhances the strengths of the individual algorithms while minimizing their individual weaknesses. Comparisons of the developed systems are made with the standard homomorphic filter architecture and similar works from the literature.