Image Processing-Based Method of Evaluation of Stress from Grain Structures of Through Silicon Via (TSV)

Author:

Sharma Manvinder1,Saripalli Sudhakara Reddy2,Gupta Anuj Kumar3,Palta Pankaj3,Pandey Digvijay4

Affiliation:

1. Department of ECE, Malla Reddy Engineering College and Management Sciences, Medchal, Hyderabad, India

2. Department of ME, Malla Reddy Engineering College and Management Sciences, Medchal, Hyderabad, India

3. Department of CSE, Chandigarh Group of Colleges, Landran, Mohali, Punjab, India

4. Department of Technical Education, U.P, I.E.T, Dr A.P.J Abdul Kalam Technical University, India

Abstract

Visualization of material composition across numerous grains and complicated networks of grain boundaries using image processing techniques can reveal fresh insights into the material’s structural evolution and upcoming functional capabilities for a variety of applications. Three-dimensional integrated circuits (3D IC) are the most practical technology for increasing transistor density in future semiconductor applications. One of the key benefits of 3D IC is heterogeneous integration, which results in shorter interconnections due to vertical stacking. However, one of the most significant challenges in building higher-density microelectronics devices is the stress generated by material mismatches in the coefficient of thermal expansion (CTE). The purpose of this study is to analyze grain boundary migration caused by variations in strain energy density using image processing methods for 3D grain continuum modeling. Temperature changes in polycrystalline structures generate stresses and strain energy densities, which may be calculated using FEM software. Single crystal Cu’s anisotropic elastic properties are twisted to suit grain orientation in space and each grain is treated as a single crystal. Grain boundary speeds are calculated using a simple model that relates grain boundary mobility to variations in strain energy density on both sides of grain boundaries. Using the grain continuum model, researchers will be able to investigate the effect of thermally generated stresses on grain boundary motion caused by atomic flux driven by strain energy. Using finite-element modeling of the grain structure in a Through Silicon Via, the stress effect on grain boundaries caused by grain rotation due to CTE mismatch was investigated (TSV). The structure must be modeled using a scanning electron microscopes Electron Backscatter Diffraction (EBSD) image (SEM). Grain growth and subsequent grain boundary rotation can be performed using the appropriate extrapolation method to measure their influence on stress and, as a result, the TSV’s overall reliability.

Publisher

World Scientific Pub Co Pte Ltd

Subject

Computer Graphics and Computer-Aided Design,Computer Science Applications,Computer Vision and Pattern Recognition

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