Electrical Characterization of Multi-Gate MOSFET with Reduced Short-Channel Effects for High-Power Applications

Abstract

The double-gate MOSFET is proposed for high-voltage and high-power applications with decreased short-channel effects (SCEs) and drain current with gate overlap. This model explicitly incorporates the SCEs for thin-layered MOSFETs with large drain regions. The device’s short-channel effects are decreased through the drain-resistance effect present in the device. The gate contact overlapped region significantly affects the device operation for high-voltage FETs. These effects are modeled by self-consistent solutions of available multigate MOSFET device models with potential distribution. The demonstrated model can be further applied for size limitations in the modeling of multigate MOSFETs.