A High Reliability Sense Amplifier for Computing In-Memory with STT-MRAM

Abstract

In the era of big data, massive data requires processing efficiently. However, the limited data bandwidth between the memory and the processor in conventional computer systems could not meet the requirement of data transferring. Computing in-memory has been considered an effective solution to address this problem. In this paper, based on the spin transfer torque-magnetic random access memory (STT-MRAM), a computing in-memory architecture with as few peripheral circuits as possible is proposed. This computing in-memory architecture gives the specific reference cell so that two rows in one array can be activated simultaneously to perform bitwise logic operations, such as OR/NOR and AND/NAND. In addition, with technology scaling down, STT-MRAM suffers from high sensitivity to process variation, which results in more device mismatch in a sense circuit. Additionally, the negative bias temperature instability (NBTI) seriously affects the life of PMOS transistors used in a sense circuit. In this paper, a high-reliability sense amplifier for computing in-memory with STT-MRAM is proposed. By using two self-enabled switching transistors, the proposed sense amplifier not only can decrease the NBTI effect on PMOS transistors but also can achieve a low sensing error rate. Using a CMOS 40[Formula: see text]nm design-kit and an accurate compact model of the STT magnetic tunnel junction (MTJ), mixed transient and statistical simulations have been present to demonstrate the functionality and performance of the proposed circuits.