Affiliation:
1. Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, Uttar Pradesh, India
Abstract
This paper presents the implementation of important full adder circuits using quantum dots (QDs) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A fair comparison among these adders shows that the mirror adder implementation in SSL paradigm does not carry any advantage over the CMOS adder in terms of complexity and number of QDs, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, static and dynamic Manchester carry gate adders in SSL reduces the complexity and number of QDs, in harmony with the trend shown in transistor adders.
Publisher
World Scientific Pub Co Pte Lt
Subject
Electrical and Electronic Engineering,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Cited by
2 articles.
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