A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules

Abstract

System-on-chip (SOC) has become a mainstream design practice that integrates intellectual property cores on a single chip. The SOC test scheduling problem maximizes the simultaneous test of all cores by determining the order in which various cores are tested. The problem is tightly coupled with the test access mechanism (TAM) bandwidth and wrapper design. This paper presents a strength Pareto evolutionary algorithm for the SOC test scheduling problem with the objective of minimizing the power-constrained test application time, wrapper design and TAM assignment in flat and hierarchical core-based systems. We demonstrate the effectiveness of the method using the ITC’02 benchmarks.