A HARDWARE IMPLEMENTATION OF THE APE100 ARCHITECTURE-Reference-Cited by-同舟云学术

A HARDWARE IMPLEMENTATION OF THE APE100 ARCHITECTURE

Published:1993-10 Issue:05 Volume:04 Page:969-976
ISSN:0129-1831
Container-title:International Journal of Modern Physics C
language:en
Short-container-title:Int. J. Mod. Phys. C

Author:

BARTOLONI A.¹²,BASTIANELLO G.¹²,BATTISTA C.¹²,CABASINO S.¹²,MARZANO F.¹²,PAOLUCCI P. S.¹²,PECH J.¹²,RAPUANO F.¹²,PANIZZI E.¹²,SARNO R.¹²,TODESCO G. M.¹²,TORELLI M.¹²,TROSS W.¹²,VICINI P.¹²,CABIBBO N.³⁴,FUCCI A.⁵,TRIPICCIONE R.⁶⁷

Affiliation:

1. Dipartimento di Fisica, Università di Roma "La Sapienza", Piazzale, A. Moro, I-00100 Roma, Italy

2. INFN, Sezione di Roma. I, Piazzale, A. Moro, I-00100 Roma, Italy

3. Dipartimento di Fisica, Università di Roma "Tor Vergata", Via E. Carnevale, I-00173 Roma, Italy

4. INFN, Sezione di Roma II, Via E. Carnevale, I-00173 Roma, Italy

5. CERN, CH-1211 Geneva 23, Switzerland

6. Dipartimento di Fisica, Università di Pisa, Via Livornese, I-56010 Pisa, Italy

7. INFN, Sezione di Pisa, Via Livornese, I-56010 Pisa, Italy

Abstract

APE100 processors are based on a simple Single Instruction Multiple Data architecture optimized for the simulation of Lattice Field Theories or other complex physical systems. This paper describes the hardware implementation of the first APE100 machine.

Publisher

World Scientific Pub Co Pte Lt

Subject

Computational Theory and Mathematics,Computer Science Applications,General Physics and Astronomy,Mathematical Physics,Statistical and Nonlinear Physics

Link

https://www.worldscientific.com/doi/pdf/10.1142/S0129183193000744

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