The electrical current characteristics of thermally annealed Co/anodic oxide layer/n-GaAs sandwich structures

Abstract

The Co/anodic oxide layer/n-GaAs MOS structures have been fabricated by us. The MOS structures have shown an excellent rectifying behavior before and after thermal annealing of 500[Formula: see text]C for 2 min. It has been stated in the literature that the thermal annealing at a relatively low-temperature can improve the quality and performance of the anodic MOS structure. The current–voltage (I–V) measurements of the annealed MOS structure have been attempted in the measurement temperature range 60–320 K with the steps of 20 K. The I–V plot at 300 K has given the diode parameter values as barrier height [Formula: see text] = 0.96 eV and ideality factor n = 1.22, diode series resistance R[Formula: see text] = 124 [Formula: see text] for the annealed sample, and [Formula: see text] = 0.87 eV and n = 2.11, R[Formula: see text] = 204 [Formula: see text] for the nonannealed structure. A mean tunneling potential barrier value of 0.59 eV for the anodic oxide layer at the Co/n-GaAs interface has been calculated from the current–voltage–temperature curves. Furthermore, [Formula: see text](T) versus (2kT)[Formula: see text] curve has followed a double Gaussian distribution (GD) of the barrier heights. It has been stated that the double GD may be originated from the presence of the surface patches and phases arisen at the anodic oxide layer/n-GaAs interface.