Study on Hierarchical Dynamic Adjustment of Integrated Circuit Flow Based on Nonlinear Detection

Abstract

In order to solve the problem that the test time is long and the test efficiency is affected in the process of IC test. With the increase in the complexity of integrated circuits, it is difficult now to diagnose the faults. To overcome this situation, there is a need to upgrade the test strategies. Based on the fault probability model, the order of test types and test vector is being adjusted. To improve the test efficiency, the high-quality test types and test vectors are loaded first, and the fault circuits are hit earlier. A hierarchical dynamic method for IC test flow is proposed. The Bayesian probability model was established by counting the failure rates of each test type and each test vector in the sample integrated circuit, and the loading sequence of each test vector was adjusted according to the probability of hitting the fault point. As the test progresses, the test data are collected constantly, the test failure rates of test type and test vector are dynamically updated, and the loading sequence of test type and test vector is adjusted synchronously. It is proved that the final circuit test time is reduced to 32.172s by the dynamic adjustment method, and the test time is reduced by 53.9%. The use of dynamically adjusted test process can find the fault circuit earlier, significantly reduce the test time of the fault circuit, and improve the test efficiency.