Investigation of Switching Sequences on a Generalized SVPWM Algorithm for Multilevel Inverters

Abstract

This paper investigates the various switching sequences on a generalized 60[Formula: see text] distributed coordinate system-based space vector pulse width modulation (SVPWM) algorithm for multilevel inverters. The main focus of this work is to improve the inverter output voltage profile by taking advantage of the redundancy inverter switching states. With the help of SVPWM algorithm, the three nearest vectors have to find out the synthesis of the [Formula: see text] location and then by applying the various optimum switching sequences, the inverter produces less harmonic content in the output voltage compared to the conventional switching sequence. All the switching sequence designs are developed with the help of minimum change detector (MCD) by using switching redundancies in order to reduce inverter switching loss. Simulation results to analyze various sequences on the general SVPWM algorithm are presented in the seven-level cascaded H-bridge (CHB) inverter. To validate the results, hardware results are presented on the seven-level CHB inverter.