ENERGY EFFICIENT REVERSIBLE BUILDING BLOCKS RESISTANT TO POWER ANALYSIS ATTACKS

Abstract

Reversible logic circuits consist of a chain of reversible gates with many stages. The existing transmission gate-based implementation of reversible gates severely suffers from voltage degradation because of the inherent resistive voltage drop when cascaded. In addition, the propagation delay increases quadratically with the number of transmission gates cascaded in reversible circuits. To circumvent these problems in cascaded circuits, static CMOS buffers or latches are generally inserted at intermediate stages. But the static CMOS latches are inherently irreversible and cannot be used in reversible circuits. In this work, a novel adiabatic reversible latch is proposed to regenerate the voltage levels at intermediate stages in cascaded reversible circuits. The proposed latch is placed at the target line of each transmission gate-based reversible gate implementation to restore the logic to their respective voltage levels and at the same time reduces the energy consumption significantly. In addition, the proposed adiabatic reversible gate implementations show resistance against power analysis attacks as the current drawn from the power supply matches for all cases of input stimulus.