FPGA Acceleration of GWAS Permutation Testing

Author:

Swiel YanivORCID,Brandenburg Jean-TristanORCID,Hayat Mahtaab,Chen Wenlong Carl,Cox Mitchell A.ORCID,Hazelhurst ScottORCID

Abstract

MotivationGenome-wide association studies (GWASs) analyse genetic variation over the genomes of many individuals in an attempt to identify single nucleotide polymorphisms (SNPs) associated with complex phenotypes. To capture a large amount of genetic variation and increase the chance of detecting associated SNPs, modern GWASs include millions of SNPs sampled from thousands of individuals. The cumulative probability of false associations increases with the number of SNPs included in the analysis. A GWAS, therefore, needs to control the number of false associations. Permutation testing is a straightforward and accurate method of controlling the false positive rate, but it is very computationally expensive (and slow) so there is a need for a permutation testing accelerator that can process modern GWAS datasets in reasonable time.ResultsFPGAs (Field-Programmable Gate Arrays) are reconfigurable integrated circuits which provide a high level of parallelisation that can be harnessed to accelerate GWAS permutation testing. This work presents an accessible FPGA-based tool (designed to run on a cloud-based AWS EC2 FPGA instance) that accelerates GWAS permutation testing for continuous phenotypes. The tool implements two known GWAS permutation testing algorithms: maxT permutation testing and adaptive permutation testing. The speed of the FPGA-based tool was compared to the speed of PLINK (a popular CPU-based tool) running on 40 Intel Xeon 4114 CPU cores using an imputed breast cancer dataset of 13.7 million SNPs sampled from 3652 individuals. For 1000 maxT permutations, the FPGA-based algorithm’s run time was 22 minutes while PLINK’s run time was almost 7 days; for 100 million adaptive permutations, the FPGA-based algorithm’s run time was 325 minutes and PLINK’s run time was about 8.5 days. For 700 million adaptive permutations of the same dataset (an almost unfeasible workload for PLINK running on a 40-core CPU) the run time of the FPGA-accelerated algorithm was 33 hours.AvailabilityAn EC2 AMI (FPGA_perm) in the us-east-1 region is available. Instructions, source code and sample data are available at https://github.com/witseie/fpgaperm.

Publisher

Cold Spring Harbor Laboratory

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