Hardware evaluation of spike detection algorithms towards wireless brain machine interfaces

Abstract

AbstractThe current trend for implantable Brain Machine Interfaces (BMIs) is to increase the channel count, towards next generation devices that improve on information transfer rate. This however increases the raw data bandwidth for wired or wireless systems that ultimately impacts the power budget (and thermal dissipation). On-implant feature extraction and/or compression are therefore becoming essential to reduce the data rate, however the processing power is of concern. One common feature extraction technique for intracortical BMIs is spike detection. In this work, we have empirically compared the performance, resource utilization, and power consumption of three hardware efficient spike emphasizers, Non-linear Energy Operator (NEO), Amplitude Slope Operator (ASO) and Energy of Derivative (ED), and two common statistical thresholding mechanisms (using mean or median). We also propose a novel median approximation to address the issue of the median operator not being hardware-efficient to implement. These have all been implemented and evaluated on reconfigurable hardware (FPGA) to estimate their hardware efficiency in an ultimate ASIC design. Our results suggest that ED with average thresholding provides the most hardware efficient (low power/resource) choice, while using median has the advantage of improved detection accuracy and higher robustness on threshold multiplier settings. This work is significant because it is the first to implement and compare the hardware and algorithm trade-offs that have to be made before translating the algorithms into hardware instances to design wireless implantable BMIs.