Simple Design Formula for Parallel Plate Mode Suppression by Ground Via-Holes in Multi-Layered Packages
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Published:2005-07-01
Issue:7
Volume:E88-C
Page:1401-1405
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ISSN:0916-8524
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Container-title:IEICE Transactions on Electronics
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language:en
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Short-container-title:IEICE Transactions on Electronics
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials