1. Baker, R J.: CMOS Circuit Design, Layout, and Simulation, 800–802, IEEE Press, 1st edn., 1998.
2. Bastos, J., Steyaert, M. and Sansen, W.: A High Yield 12-bit 250-MS/s CMOS D/A Converter, IEEE Cust. Integr. Cir., 431–434, 1996.
3. Bastos, J., Marques, A. M., Steyaert, M. S. J. and Sansen W.: A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC, IEEE J. Solid.-St. Circ., 33, 1959–1969, 1998.
4. Chen, T. and Gielen, G. G. E.: A 14-bit 200-MHz current-steering DAC with switching-sequence post-adjustment calibration, IEEE J. Solid.-St. Circ., 42, 2386–2394, 2007.
5. Cong, Y. and Geiger, R L.: Formulation of INL and DNL yield estimation in current-steering D/A converters, Proc. Iscas., 3, 149–152, 2002.