High Speed and Less Area Efficient Montgomery Modular Multiplication for VLSI Applications

Abstract

A high speed and area efficient Montgomery modular multiplication algorithm is implemented. In the proposed multiplier high speed is achieved by using the carry save adder (CSA) to reduce the carry propagation at the addition operation stage due to this delay is reduced and the input and outputs are propagated in the binary format. In modular multiplication these carry save adders are used for the format conversion leads less area consumption and the critical path is also reduced. In the proposed multiplier the number of addition and multiplication stages is reduced at the each stage of computation with the use of parallelism. The proposed multiplier is designed in the Xilinx ISE tool with the use of Verilog HDL programming language. Tentative results shows that the proposed Montgomery modular multiplication achieves better performance with respect to area and delay while comparing with the previous Montgomery modular multiplication.