Effects of Process Variations on Silicon Carbide Devices for Extreme Environments

Abstract

The variation in device process parameters is a core issue in the realisation of complex SiC logic for extreme environments. Factorial design was used to study the effect of variation in four key process parameters on the threshold voltage of an n-channel lateral JFET. Each parameter is simultaneously varied by +/-10% from the default value and the individual and combined effects were calculated at 300, 600 and 1000K. Consequently, we show how these variations in device parameters degrade the threshold voltage, VI, and, hence, the noise margin of logic inverter.