Implications of Threshold-Voltage Instability on SiC DMOSFET Operation

Abstract

Although recent fast I-V measurements and subthreshold analysis reveal that the threshold-voltage instability due to low-field bias stressing at room temperature is greater than previously reported when calculated using slower, standard measurements by a parameter analyzer—a result that is consistent with electrons directly tunneling into and out of near interfacial oxide traps, this effect will not prevent the use of power SiC DMOSFET switches in power converter applications if certain precautions are followed. Namely, if the threshold voltage is set high enough so that a negative shift in threshold voltage will not increase the leakage current in the off-state, then the primary effect will be to increase the on-state resistance by decreasing the effective gate voltage. The instability due to ON-state stressing is greater than that for bias stressing alone, but not significantly. For a well behaved device, a 1-hour ON-state stress will result in about a 7 percent increase in conduction losses, which is manageable for power converter applications.