Process Antenna Effect Elimination in Ultra Deep Submicron

Abstract

This paper analyzes the mechanism of process antenna effect in ultra deep submicron IC physical design and provides the antenna ratio calculation method. A new elimination method of process antenna effect combined with clock tree synthesis is proposed. The elimination method minimizes the impact to the clock latency and clock skew by setting up reasonable constraint for clock tree synthesize. Finally, the elimination method is used during place and route of the physical design of a reconfigurable video decoder chip, which is based on TSMC 65nm low power technology. The proposed method eliminates the process antenna effect of the design effectively, also minimizes the impact to clock tree and chip timing to the least.