Power MOSFET Devices and ESD Reliability Evaluations

Abstract

The electrostatic discharge (ESD) reliabilities in different power MOSFETs will be investigated in this paper. From the experimental results, ESD zap pulses at the gate terminal will cause electrons or holes trap in the gate oxide and loss the Si-SiO2 interface integrity, especially for the 100V nDEMOS, 200V nDEMOS, and IRF640, in which they do not have any ESD protection strategy. Electrons or holes trapped in the gate SiO2 layer will be caused the transconductance (Gm) or threshold voltage (Vth) of a MOSFET increasing or reduction, and which is resulted from electron mobility degradation. The RFW2N06RLE and RLD03N06CLE power VDMOS ICs, which with different kinds of ESD protection circuit, are less influenced by ESD pulses experimentally.