Synergy Micro-Electronics Technology with a High Linearity BiCMOS Sample-and-Hold Circuit

Author:

Lin Jie1,Mu Fei Yan2

Affiliation:

1. Synergy Micro-Electronics Technology Co., Ltd.

2. Chengdu College of UESTC

Abstract

A high accuracy BiCMOS sample and hold (S/H) circuit employed in the front end of a12bit 10 MS/s Pipeline ADC is presented. To reduce the nonlinearity error cause by the sampling switch, a signal dependent clock bootstrapping system is introduced. It is implemented using 0.6 um BiCMOS process. An 88.77 dB spurious-free dynamic range (SFDR), and a -105.20 dB total harmonic distortion (THD) are obtained.

Publisher

Trans Tech Publications, Ltd.

Reference7 articles.

1. K. R. Stafford, R.A. Blanchard, P.R. Gray. A completemonolithic sample/hold amplifier,. IEEE J. Solid-State Circuits, Jul. 1974 . vol. SSC-9, no. 6 p.381–387.

2. D.A. Johns, K. Martin, Analog Integrated Circuit Design. Toronto: John Wiley & Sons, Inc. 1997. 8, pp.334-365.

3. .

4. A. Boni , A. Pierazzi, and C. Morandi, A 10-b 185-MS/s track-and-hold in 0. 35-μm CMOS,. IEEE J. Solid-State Circuits, vol. 36, Feb 2001, p.195–203.

5. YANG Bin, YIN Xiumei, YANG Huazhong. A High-speed High-Resolution Sample-and-Hold Circuit,. Chinese Journal of Semiconductors, 2007, 28(10), pp.1642-1646.

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