Optimization Algorithm Analysis for FIR Filter by FPGA-Reference-Cited by-同舟云学术

Optimization Algorithm Analysis for FIR Filter by FPGA

Published:2013-08 Issue: Volume:373-375 Page:1269-1273
ISSN:1662-7482
Container-title:Applied Mechanics and Materials
language:
Short-container-title:AMM

Author:

Shen Zhao Jun¹,Xu Sen¹

Affiliation:

1. YANCHEN Institute

Abstract

The article introduces essential method to realize the high accuracy and velocity FIR filter by FPGA. Proposes the FIR filter optimization scheme design of serial shifts based on FPGA. Avoided the shortcoming of the traditional parallel algorithm module taking the massive hardware resources . And give 11-order and 8-bits low pass filter design as the specific research object. Realized the partial functions which the traditional numeral FIR filter cannot.May adjusts the filter exponent number conveniently and suits different application.

Publisher

Trans Tech Publications, Ltd.

Link

https://www.scientific.net/AMM.373-375.1269.pdf

Reference4 articles.

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2. LiuAiRong, Zhencheng Wang. EDA technique and CPLD/FPGA development tutorials. Beijing: Tsinghua University Press, (2010).

3. Hanho Lee, Sobelman G E. Performance Evaluation and Optimal design for FPGA- based Digit- serial DSP Functions [J ] . Computers and Electrical Engineering , 2009 , 29 : 357 - 377.

4. Guo Jichang, XiangHui. FIR filter design based on FPGA device [J]. Electronic technology applications, 2010, 26.

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