1. Fangyong Hou, Hongjun He, Nong Xiao, Fang Liu. Bus and memory protection through chain-generated and tree-verified IV for multiprocessor systems [J]. Future Generation Computer Systems. 2013: 901-912.
2. ZHANG Yi-wei, Wu Ke-ke, CHEN Jia-pei. Security Chip Memory Bus for Resisting Invasive Analysis[J]. Journal of Chinese Computer Systems, 4(33), 2012: 785-788.
3. Best. R. M. Microprocessor for Executing Enciphered programs [P]. U. S. Patent No. 4 168 396. September 18, (1979).
4. Richard Takahashi, Daniel N. Heer. Secure memory management unit for microprocessor [P]. U.S. Patent No. 5 825 878. October 20, (2005).
5. Brant Candelore, Eric Sprunk. Secure processor with external memory using block chaining and block reordering [P]. U.S. Patent No. 6 0661 449. May 9, (2007).