Parallel Implementation of High Speed Mono-Pulse Angle Estimation Processor Based on Multi-IC Architecture-Reference-Cited by-同舟云学术

Parallel Implementation of High Speed Mono-Pulse Angle Estimation Processor Based on Multi-IC Architecture

Published:2013-11 Issue: Volume:846-847 Page:1225-1229
ISSN:1662-8985
Container-title:Advanced Materials Research
language:
Short-container-title:AMR

Author:

Bi Yan Xian¹,Zhang Yu Xi¹,Yuan Chang Shun¹,Zhang Yu Xian²

Affiliation:

1. Beihang University

2. Automatic Control and Computer Simulation

Abstract

This paper proposes a kind of high speed mono-pulse sum-difference angle estimation hardware architecture. Sum-difference amplitude mono-pulse algorithm is implemented in the hardware which is composed of 4 chips of XC6VSX315T and three chips of TMS320C6678. This hardware structure has already been applied in engineering.

Publisher

Trans Tech Publications, Ltd.

Subject

General Engineering

Link

https://www.scientific.net/AMR.846-847.1225.pdf

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