Salicide-Like Process for the Formation of Gate and Source Contacts in 4H-SiC TSI-VJFETs

Abstract

The self-aligned approach allowed to fabricate 4H-SiC VJFETs with conventional contact lithography with only 4 lithography steps. The main problem of this approach was the gate-source leakage current. In order to address this issue, a salicide process has been adopted resulting in a substantial reduction of the gate-source leakage current. The success of this approach paved the way for fabricating high power 4H-SiC devices with extremely low fabrication cost.