High Quality 4H-SiC Epitaxial Layer by Tuning CVD Process

Abstract

In this work many steps concerning the epitaxial layer growth on 4H-SiC are studied, evaluated and optimized to obtain high quality 4H-SiC epitaxy. The processes evaluated have been studied on a Hot Wall CVD reactor. The first step related to the substrate surface etching has been tuned by choosing the H2 flow, temperature and process time at which most of defects (mainly stacking faults) are not propagated. Then, the buffer layer step has been optimized by increasing the thickness at which an effective reduction of defect density and an improved electrical performance of power devices have been detected. Also, during the buffer layer growth a strong dependence between basal plane dislocations propagation and the growth rate has been observed. A crucial step carefully studied has been the drift layer growth. It was optimized by increasing the growth rate (13<GR<15µm/h) that results in a lower defectiveness, good thickness and doping uniformity. Final stage concerning the cooling of the process has been strongly revisited. A significant decreasing of the morphological defects (carrots, pits) and stacking faults has been observed by slowing the cool down process (~ 25 °C/min).