Another Implementation of Efficient Recoding Circuit for Signed Digit to Residue Canonical Signed Digit on Modulo 2<sup>n</sup>-1-Reference-Cited by-同舟云学术

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Another Implementation of Efficient Recoding Circuit for Signed Digit to Residue Canonical Signed Digit on Modulo 2ⁿ-1

Published:2019-02 Issue: Volume:888 Page:78-82
ISSN:1662-7482
Container-title:Applied Mechanics and Materials
language:
Short-container-title:AMM

Author:

Tanaka Yuuki¹

Affiliation:

1. Gunma University

Abstract

In this paper, we propose an efficient SD-to-RCSD recoding circuit structure on modulo. This structure is based on the parallel prefix addition circuit, that is, a carry for each digits is precalculated in parallel.

Publisher

Trans Tech Publications, Ltd.

Link

https://www.scientific.net/AMM.888.78.pdf

Reference13 articles.

1. R. Zimmermann, Efficient VLSI implementation of modulo (2n ± 1) addition and multiplication,, Proc. 14th IEEE Symposium on Computer Arithmetic, pp.158-167, (1999).

2. A. Spyrou, D. Bakalis, and H. T. Vergos, Efficient architectures for modulo 2n − 1,, 2009 16th International Conference on Digital Signal Processing, pp.1-6, (2009).

3. Z. Wang, G. A. Jullien, and W. C. Miller, An algorithm for multiplication modulo (2n − 1),, Proc. 39th IEEE Midwest Symp. on Circuits Syst, Vol.3, pp.1301-1304, (1996).

4. A. Herrfeld, S. Hentschke, Look-ahead circuit for csd-code carry determination,, Electronics Letters, 31 (6), pp.434-435, (1995).

5. Ç. K. Koç, Parallel canonical recoding,, Electronics Letters, 32 (22), pp.2063-2065, (1996).

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