Abstract
In this paper a method for synthesizing Reduced Multi-Valued Logic Networks (RMVLNs) using NZMDD is presented. MVL functions represented as large MVLNs are reduced by RMVLN. The detailed working of NZMDD method is presented elaborately in this paper. It is observed that reduced average Product Term (PT) is achieved in MVL synthesis using NZMDD. Experimental analysis is carried out by examining randomly generated 49998 non-sequential benchmark circuits. An improvement average PT reduction of 12.486% is noted in comparison to evolutionary ACO-MVL algorithm.
Publisher
Trans Tech Publications, Ltd.
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