Use N+ Buried Layer to Design a Low On-Resistance VDMOS-Reference-Cited by-同舟云学术

Use N+ Buried Layer to Design a Low On-Resistance VDMOS

Published:2013-09 Issue: Volume:756-759 Page:4267-4270
ISSN:1662-8985
Container-title:Advanced Materials Research
language:
Short-container-title:AMR

Author:

Tang Zhao Huan¹,Wang Bin²,Wang Jia Nan²,Tan Kai Zhou¹

Affiliation:

1. Science and Technology on Analog Integrated Circuit Laboratory

2. Sichuan Institute of Solid-State Circuits

Abstract

A novel structure of a VDMOS in reducing on-resistance is proposed and experimentally demonstrated with a 200V N-channel VDMOS. With this structure, the on-resistance value of the VDMOS is reduced by 19.6% than that of a traditional VDMOS structure as the breakdown voltage almost maintained the same value, and there is only one additional mask in processing this new structure VDMOS, which is easily fabricated. By TCAD tool, the specific on-resistance value will reduce by 23%, and the value by 33% will be realized when the device is fabricated in three epitaxies and four buried layers. The novel structure can be widely used in high-voltage VDMOS and BCD areas.

Publisher

Trans Tech Publications, Ltd.

Subject

General Engineering

Link

https://www.scientific.net/AMR.756-759.4267.pdf

Reference7 articles.

1. SeongDong Kim, Iljung Kim, Minkoo Han, et al: Solid-State Electronic. Forum Vol. 38-2(1995), p.345.

2. Vrej Barkhordarian, International Rectifier, El Segundo, Ca. Power MOSFET Basics.

3. Sze S M: Physics of Semiconductor Devices . Second Edition, 1981: 222.

4. Jiang Yan, Chen Long, Shen Keqiang: Chinese Journal of Electron Device. Forum Vol. 31-2 (2008), p.357.

5. Yuan Shoucai, Liu Yamei: Journal of Electron Device. Forum Vol. 31-4 (2008), p.1219.