Affiliation:
1. National University of Defense Technology
2. University of College Cork
Abstract
Power gating has become a popular technique to reduce the ever-increasing leakage power for commercial microprocessors or SoCs, however the wakeup energy and delay cost harm its performance. This paper proposes a fast reactivation scheme to reduce the transition delay and energy. The experiment results show that, comparing to the traditional power gating implementation, it can achieve 19.66% reactivation energy reduction, 9.28% peak leakage reduction, and 23.36% wakeup delay reduction, at the cost of 2.75% area increasing.
Publisher
Trans Tech Publications, Ltd.
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