Abstract
Counter-based Digital PWM (DPWM), the simplest DPWM device, can be easily implemented only by a counter and a comparator; however, the resolution of the counter-based DPWM is directly proportional to its input reference clock, and thus the higher clock frequency is required, which means higher dynamic power consumption and noise interference may be incurred. In this paper, without increasing the reference clock frequency, a new design approach using capacitor integration is proposed to extend the resolution of the counter-based DPWM, and it also can reduce the hardware complexity compared with the delay-line DPWM.
Publisher
Trans Tech Publications, Ltd.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献