Analytical Threshold Voltage Models for Strained Si/Strained Si1-xGex/Relaxd Si1-yGey PMOSFET

Abstract

Threshold voltage models for both buried channel and surface channel for the dual-channel strained Si/strained Si1-xGex/relaxd Si1-yGey(s-Si/s-SiGe/Si1-yGey) p-type metal-oxide-semiconductor field-effect transistor (PMOSFET) are presented in this paper. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel, because the hole mobility in the buried channel is higher than that the surface channel. They offer a good accuracy as compared with the results of device simulator ISE.