Low Frequency Noise in 4H-SiC Lateral JFET Structures

Abstract

Low frequency noise on 4H-SiC low-level signal-lateral JFETs was systematically investigated. In contrast to previous studies, which are based upon high power vertical structures, this work investigates the low-frequency noise behaviour of low-level signal-lateral devices which are more relevant to the realisation of small signal amplifiers.The JFETs studied share an identical cross section, with different gate lengths and widths. For high temperature operation between 300K and 700K at VGS = 0V, the Normalised Power Spectral Density (NPSD) of the JFETs is proportional to ƒ-1. The NPSD increases monotonically with temperature until a critical temperature, where it starts to decline. Two unique noise origins, fluctuation from bulk and SiO2-SiC interface traps were observed across all the devices investigated. Low frequency noise for devices with a 50μm gate width is localised at the SiO2-SiC interface, whereas for wider devices the noise is seen to be of bulk/substrate origin, which follows Hooge’s model.