The Influence of Gate Material, SiO2 Fabrication Method and Gate Edge Effect on Interface Trap Density in 3C-SiC MOS Capacitors

Abstract

This paper reports on results of interface trap analysis of 3C-SiC MOS capacitors fabricated using four different gate materials and two SiO2 oxide preparation methods. The results indicate that post-deposition annealing in wet oxygen of PECVD deposited SiO2 samples increases the near-interface or slow trap densities, compared with wet oxygen thermally oxidized samples. It has also been found that the energy distribution, Dit, of electron states at the oxide/SiC interface of MOS capacitors with different sizes depend on the factor R=P/A, where P stands for the gate perimeter and A for the gate area, which is related to the amount of stress under the edge of the metallic gate.