Research of Design Technology of Reconfigurable Shift Unit Based on Multilevel Interconnection

Author:

Su Yang1,Dai Zi Bin1,Li Wei1

Affiliation:

1. Zhengzhou Information Science and Technology Institute

Abstract

Design proposal of reconfigurable shift unit based on multilevel interconnect barrel shifter is presented, which can support 8~32 bit wide and any variable length between 1 bit and 31 bit. Through adding expander circuit, the width of this unit can broaden to 8~128bit. The design has been realized using Altera’s FPGA and synthetized and optimized on Synopsys’s Design Compiler. The result proves that the maximum frequency can achieve 400MHz on 0.13µm CMOS technology.

Publisher

Trans Tech Publications, Ltd.

Subject

General Engineering

Reference6 articles.

1. Zeghid Medien, Mohsen Machhout, Design and Hardware Implementation of QoSS-AES Processor for Multimedia applications, TRANSACTIONS ON DATA PRIVACY 3(2010)43-64.

2. YU XUERONG, DAI ZIBIN, Design and Implementation of Reconfigurable Shift Unit, Information Security, 1008-0570(2007)02-3-0065-02.

3. Zeng RuiHuai, Zhong DongQin, The Research of Shifter of 16bit DSP Processor, 2006, http: /www. elecfans. com.

4. Ray C. C cheung, Wayne Luk, Peter Y.K. cheung, Reconfigurable Elliptic Curve Cryptosystems on a Chip, Design, Automation and Test in Europe. 2005, Proceedings, 1530-1591/05.

5. M. Aqeel Iqbal, RFU Based Computational Unit Design For Reconfigurable Processors, World Academy of Science, Engineering and Technology 50 (2009).

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