A Low-Power ΣΔ Modulator Using Asynchronous SAR Quantizer for Sensor Application

Abstract

This paper presents a low power ΣΔ modulator for a low power microsensor application. The ΣΔ modulator adopts second-order single loop topology with input feed-forward path. An asynchronous 4-bit successive approximation (SAR) quanztizer is employed to digitize the analog input. Inherent summation of SAR quantizer is utilized as analog summation. The switched operational amplifier is used in first integrator to reduced power consumption. The modulator, simulated at the transistor level using 0.13-μm CMOS technology, obtains a peak SNDR of 93 dB over an input signal of 5 kHz and simulation power consumption is 340 μW from 1-V supply.