Leakage Process and Minimization -Transistor Stacking Effect, Data Retention Gated Ground Cache, Drowsy Cache

Abstract

Leakage Current is found to be gradually increasing in CMOS VLSI circuits with advance of technologies, specially in nanometer range. Though area of a transistor is becoming less and lesser, but precious control over the operations of a transistor is not possible in such a small structure. Reductions of threshold voltage, channel length, and gate oxide thickness are responsible for generation of leakage current. In this paper we have reviewed eight types of leakage current present in CMOS VLSI circuits, namely 1. Reverse Bias pn Junction Current, 2. Sub-threshold Leakage, 3. Drain Induced Barrier Lowering Effect, 4. Gate Induced Drain Leakage current, 5. Punch Through, 6. Narrow Channel Effects, 7. Gate Oxide Tunneling leakage current and 8. Hot-Carrier Injection. After that, we have reviewed 6-T SRAM read and write operation. Next to that, we have reviewed three techniques of leakage reduction namely 1. Transistor Stacking Effect, 2. Data Retention Gated-Ground Cache and 3. Drowsy Cache. We have reproduced the simulation result of these leakage minimization techniques. Finally we have shown comparison of 1. Conventional 6-T SRAM leakage current, 2. leakage current using Data Retention Gated-Ground Cache techniques and 3. leakage current using Drowsy Cache techniques. To obtain these three results we have used Cadence Virtuso & SoC Encounter tools. All these three results has been simulated with IBM 90 nanometer technology file.