Affiliation:
1. Soitec
2. Fraunhofer Institute for Integrated Systems and Device Technology (IISB)
Abstract
The Smart CutTM technology enables the combination of a high quality single crystal SiC layer onto a low resistivity handle wafer (<5mOhm.cm), allowing device optimization as well as the reduction of device’s conduction and switching losses. On this new SmartSiCTM substrate, the sheet resistance of the back side contact after metal deposition, without anneal, is about 10x lower than the annealed back side contact on 4H-SiC. Schottky-barrier vertical structures thinned down to 250μm were prepared for power cycling tests (PCT) measurements. Up to 250 k cycles, the devices remained within the specifications of AQG324 for samples prepared from SmartSiCTM substrates. We are demonstrating here that in addition to a higher current rating (up to 20%), the SmartSiCTM substrate enables a device fabrication simplification by skipping the annealing of the back-side ohmic contact, without compromising either the back-side contact resistance or the assembly PCsec reliability.
Publisher
Trans Tech Publications, Ltd.
Subject
Mechanical Engineering,Mechanics of Materials,Condensed Matter Physics,General Materials Science
Reference8 articles.
1. S. Rouchier et al., in Materials Science Forum 1662-9752, Vol. 1062, pp.131-135
2. U. Scheuermann et al., Microelectronics Reliability 2010;50(9-11):1203–9
3. E. Guiot et al., in proceedings of APEC2022, March (2022)
4. C. Hellinger et al., Materials Science Forum, Vol. 1004, pp.718-724
5. E. Guiot et al., in proceedings of PCIM 2022, May 2022.
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献