COMPONENTS OF HARDWARE NEURAL NETWORKS FOR COORDINATED PARALLEL-VERTICAL DATA PROCESSING IN REAL TIME

Abstract

It is shown that for the pro­ces­sing of in­tensi­ve da­ta flows in in­dustry (ma­na­ge­ment of techno­lo­gi­cal pro­ces­ses and complex ob­jects), energy (op­ti­mi­za­ti­on of lo­ad in po­wer grids), mi­li­tary af­fa­irs (techni­cal vi­si­on, mo­bi­le ro­bot traf­fic control, cryptog­raphic da­ta pro­tec­ti­on), transport (traf­fic ma­na­ge­ment and en­gi­ne), me­di­ci­ne (di­se­ase di­ag­no­sis) and instru­men­ta­ti­on (pat­tern re­cog­ni­ti­on and control op­ti­mi­za­ti­on) the re­al-ti­me hardwa­re neu­ral net­works with high ef­fi­ci­ency of eq­uipment use sho­uld be appli­ed. The ope­ra­ti­onal ba­sis of neu­ral net­works is for­med and the fol­lo­wing ope­ra­ti­ons are cho­sen for hardwa­re imple­men­ta­ti­on: the se­arch of the ma­xi­mum and mi­ni­mum val­ues, cal­cu­la­ti­on of the sum of squa­res of dif­fe­ren­ces and sca­lar pro­duct. Req­ui­re­ments for hardwa­re com­po­nents of neu­ral net­works with co­or­di­na­ted ver­ti­cal-pa­ral­lel da­ta pro­ces­sing are de­ter­mi­ned, the ma­in ones of which are: high ef­fi­ci­ency of eq­uipment use, adap­ta­ti­on to the req­ui­re­ments of spe­ci­fic appli­ca­ti­ons, co­or­di­na­ti­on of in­put da­ta in­tensity with the com­pu­ta­ti­on in­tensity in hardwa­re com­po­nent, re­al-ti­me ope­ra­ti­on, struc­tu­ral fo­cus on VLSI imple­men­ta­ti­on, low de­ve­lop­ment ti­me and low cost. It is sug­gested to eval­ua­te the de­ve­lo­ped hardwa­re com­po­nents of neu­ral net­works ac­cording to the ef­fi­ci­ency of the eq­uipment use, ta­king in­to ac­co­unt the comple­xity of the com­po­nent imple­men­ta­ti­on al­go­rithm, the num­ber of ex­ternal in­terfa­ce pins, the ho­mo­ge­ne­ity of the com­po­nent struc­tu­re and re­la­ti­onship of the ti­me of ba­sic neu­ro-ope­ra­ti­on with the eq­uipment costs. The ma­in ways to control the in­tensity of cal­cu­la­ti­ons in hardwa­re com­po­nents are the cho­ice of the num­ber and bit ra­tes of da­ta pro­ces­sing paths, chan­ging the du­ra­ti­on of the work cycle by cho­osing the spe­ed of the ele­ment ba­se and the comple­xity of ope­ra­ti­ons imple­men­ted by the con­ve­yor. The pa­ral­lel ver­ti­cal-gro­up da­ta pro­ces­sing met­hods are pro­po­sed for the imple­men­ta­ti­on of hardwa­re com­po­nents of neu­ral net­works with co­or­di­na­ted pa­ral­lel-ver­ti­cal control pro­ces­sing, they pro­vi­de control of com­pu­ta­ti­onal in­tensity, re­duc­ti­on of hardwa­re costs and VLSI imple­men­ta­ti­on. A pa­ral­lel ver­ti­cal-gro­up met­hod and struc­tu­re of the com­po­nent of cal­cu­la­ti­on of ma­xi­mum and mi­ni­mum num­bers in ar­rays are de­ve­lo­ped, due to pa­ral­lel pro­ces­sing of a sli­ce from the gro­up of di­gits of all num­bers it pro­vi­des re­duc­ti­on of cal­cu­la­ti­on ti­me ma­inly de­pen­ding on bit si­ze of num­bers. The pa­ral­lel ver­ti­cal-gro­up met­hod and struc­tu­re of the com­po­nent for cal­cu­la­ting the sum of squa­res of dif­fe­ren­ces ha­ve be­en de­ve­lo­ped, due to pa­ral­le­li­za­ti­on and se­lec­ti­on of the num­ber of con­ve­yor steps it en­su­res the co­or­di­na­ti­on of in­put da­ta in­tensity with the cal­cu­la­ti­on in­tensity, re­al-ti­me mo­de and high eq­uipment ef­fi­ci­ency. The pa­ral­lel ver­ti­cal-gro­up met­hod and struc­tu­re of sca­lar pro­duct cal­cu­la­ti­on com­po­nents ha­ve be­en de­ve­lo­ped, the cho­ice of bit pro­ces­sing paths and the num­ber of con­ve­yor steps enab­les the co­or­di­na­ti­on of in­put da­ta in­tensity with cal­cu­la­ti­on in­tensity, re­al-ti­me mo­de and high ef­fi­ci­ency of the eq­uipment. It is shown that the use of the de­ve­lo­ped com­po­nents for the synthe­sis of neu­ral net­works with co­or­di­na­ted ver­ti­cal-pa­ral­lel da­ta pro­ces­sing in re­al ti­me will re­du­ce the ti­me and cost of the­ir imple­men­ta­ti­on.