Survey: Performance Analysis of FIR Filter Design Using Modified Truncation Multiplier with SQRT based Carry Select Adder

Abstract

A recent years of technology development in Signal processing application a FIR (Finite impulse response) filter design will have a highly compactable with high performance and low power in all digital signal processing application, such as audio processing, signal processing, software define radio and so on. Now a days in our environment will have more signal noises, and fluctuation due to technology development, here the Filter design is mainly configuring the priority to reduce the signal noises and fluctuation in all type of gadgets. In this project, the design contains Transpose form of high performance and high speed filter design using finite impulse response (FIR) filter with technique of pipelined inherently and supported multiple constant multiplication (MCM) in significant with saving power computation. In digital signal processing, the multiplier is a highly required thing, the example of parallel multiplier provide a high-speed and highly reliable method for multiplication, but this parallel multiplier will take large area and also power consumption. In the FIR filter design, multiplier and adders is the maximum priority will take to give the performance, but this MCM multiplier and Adders tree architecture will take large area and maximum power consumption in signal processing. So our Proposed approach of this work, will have replace the MCM multiplier to Truncated Multiplier and using the technique of Truncated based both Signed and Unsigned Operation with SQRT based Carry Select Adder (CSLA), and also replace the normal adders in FIR Filter to SQRT based Carry Select Adder (CSLA). In the proposed system of FIR Filter design results to be analysis with signed and unsigned Truncation using modified technique of HSCG-SCS based SQRT-CSLA and hence proved its more efficient than existing design, such as FIR filter for Truncation multiplier with SQRT-CSLA based Adders, FIR filter for Truncation multiplier with BEC based Adders, FIR filter for Truncation multiplier with RCA, and FIR filter for Truncation multiplier with Common Boolean logic based RCA, and finally implemented this design on VHDL with help of Xilinx FPGA-S6LX9 and shown the performance of proposed design in terms of delay, area, and power.