The reordered deblocking filter and SAO architecture for HEVC system

Abstract

High Efficiency Video Coding (HEVC) used in broad band and wireless applications employs two in-loop filters to remove the blurring artifacts, blocking artifacts and ringing artifacts. The standard h.264/AVC deblocking filter which requires more memory initially filters the horizontal borders, followed by the vertical borders. The results of vertical borders filtering are utilized in the horizontal filtering process and the obtained results are further stored in temporary memory. The proposed system comprises of a reordering filter to reduce the order of the filter and a SAO to modify the decoded samples to a new offset value inorder to perform robust encryption mechanism. Hence reorder filter reduces the memory needed for this filtering process. In HEVC, SAO is an in-loop filter and located next to deblocking filter. The idea of SAO is to compensate renovated samples by adding an offset to each pixel, so that the distortion between renovated picture and original one can be reduced. Implementation of proposed simulation work is done by Verilog HDL and implemented using Virtex 6 FPGA to compute the power and hardware requirements in terms of LUT and slice registers.