Multi-column parallel QC-LDPC decoder architecture for NAND flash memory-Reference-Cited by-同舟云学术

Multi-column parallel QC-LDPC decoder architecture for NAND flash memory

Published:2018 Issue:10 Volume:15 Page:20180397-20180397
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Shen Wei¹,Chen Cheng²,Sha Jin³

Affiliation:

1. School of Electrical Science and Engineering, Nanjing University

2. Microelectronics R&D Institute, ZTE Corporation

3. Shenzhen Research Institute, Nanjing University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/15/10/15_15.20180397/_pdf

Reference11 articles.

1. [1] G. Dong, et al.: “Using data postcompensation and predistortion to tolerate cell-to-cell interference in MLC NAND flash memory,” IEEE Trans. Circuits Syst. I, Reg. Papers 57 (2010) 2718 (DOI: 10.1109/TCSI.2010.2046966).

2. [2] K. Kim: “Technology for sub-50 nm DRAM and NAND flash manufacturing,” IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest (2005) 323 (DOI: 10.1109/IEDM.2005.1609340).

3. [3] J. Li, et al.: “Realizing unequal error correction for NAND flash memory at minimal read latency overhead,” IIEEE Trans. Circuits Syst. II, Exp. Briefs 61 (2014) 354 (DOI: 10.1109/TCSII.2014.2312640).

4. [4] R. Gallager: “Low-density parity-check codes,” IRE Trans. Inf. Theory 8 (1962) 21 (DOI: 10.1109/TIT.1962.1057683).

5. [5] M. P. C. Fossorier, et al.: “Reduced complexity iterative decoding of low-density parity check codes based on belief propagation,” IEEE Trans. Commun. 47 (1999) 673 (DOI: 10.1109/26.768759).